Design of AI Hardware Accelerator of Various Deep Neural Networks using Verilog HDL.

• [Basic Fully-connected Network]
  - 서정윤, 이종윤, 박성준, 이하림, "Implementation and Evaluation of fully-connected network on Hardware using Verilog HDL," 한국정보기술학회 하계학술대회, 2024.
  - J. Y. Lee, J. Y. Seo, S. J. Park, H. Lee, and Y. H. Lee, "Hardware Accelerator for Real-time Image Classification," The 2024 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, USA, Dec. 11-13, 2024 [Scopus].

• [Lightweight Fully-connected Network][Quantization][LRA] J. Y. Seo, J. Y. Lee, H. Lee, "Design of Lightweight Fully-connected Network in Hardware using Learning-based Low-rank Approximation and Quantization Techniques," The Transactions of the Korean Institute of Electrical Engineering, 2025 [Scopus].

• [CNN] J. Y. Lee, J. Y. Seo, S. J. Park, H. Lee*, "Design of Hardware Accelerator of Convolution Layer using Verilog HDL," The Transactions of the Korean Institute of Electrical Engineers (KIEE), 2025 [Scopus].

• [Transpose Convolution] J.Y. Lee(=), J.Y. Seo(=), H. Lee, and H. W. Lee, "Implementation of Transpose Convolution Layer on FPGA,"  12th International Conference on Electrical and Electronics Engineering (ICEEE), Istanbul, Turkey, Sept. 24-26, 2025 (= means "equal contribution").

H/W oriented Activation Function effectively to reduce the required number of bits for feature maps generated between Neural Layers.

• Research grant for master's degree students, National Research Foundation of Korea, 2024 (link) (link).

• [Learnable Activation Function with limited upper and lower values] 서정윤, 이하림, "A Learnable Activation Function to Limit Feature Values for Bit Efficiency," 한국통신학회 하계학술대회, 2025.

  1.  "Development of a learnable activation function for optimal upper and lower values to reduce the required number of bits on memory and bus interface".

Development of Various Intelligent Systems using Various Deep Learning Networks.

• FATHER: Finding and Tracking Hidden pERson with Object Detection and Face Similarity.

  1. 서정윤, 박성준, 이하림, "Implementation of Deep-Learning based Specific Person Identification System using Facial Similarity," 한국통신학회 동계학술대회, 2024.

• R²Sys-FTCP: Recognition and Recommendation System for Fitness Exercise Types and Correct Posture.

Intelligent High-precision GPS scheme using Deep Learning, 2022, Campus Patent Universiade.

Samsung AI Challenge (3D Metrology), 2022, DACON.

Research grant for master's degree students, National Research Foundation (NRF) of Korea, 2024 (12 million won) (link) (link).

Capstone Design Fair, "Finding and Tracking Hidden pERson with Object Detection and Face Similarity," Silver Prize, 2023. 

Campus Patent Universiade, "Intelligent High-precision GPS scheme using Deep Learning," Encouragement Prize, 2022 (link).

단말기 중심 위치 측위를 위한 딥러닝 네트워크 기반 오차 보정 정보 생성 기법

Real-time Segmentation System for Autonomous Driving Vehicle

• 박성준, 이하림, "Performance Evaluation of Fully Convolutional Network for Autonomous Driving with the Latest Car Daytime Road Data," 한국정보기술학회 하계학술대회, 2024.

• 박성준, 이하림, "Improvement of Performance and Processing Speed in Semantic Segmentation Network Models Using RepBlock," 한국통신학회 하계학술대회, 2025.

Design of ConvTransopose2D layer for Generative AI.

• [Full-connected Layer] J. Y. Lee, J. Y. Seo, S. J. Park, H. Lee, and Y. H. Lee, "Hardware Accelerator for Real-time Image Classification," The 2024 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, USA, Dec. 11-13, 2024 [Scopus].

• [Basic Fully-connected Network] 서정윤, 이종윤, 박성준, 이하림, "Implementation and Evaluation of fully-connected network on Hardware using Verilog HDL," 한국정보기술학회 하계학술대회, 2024.

• [CNN] J. Y. Lee, J. Y. Seo, S. J. Park, H. Lee*, "Design of Hardware Accelerator of Convolution Layer using Verilog HDL," The Transactions of the Korean Institute of Electrical Engineers (KIEE), 2025 [Scopus].

ADsP (Advanced Data Analytics Semi-Professional, 빅데이터[준전문가]), 2025.

Capstone Design Fair, "Finding and Tracking Hidden pERson with Object Detection and Face Similarity," Silver Prize, 2023. 

Design of AI Hardware Inference using Verilog HDL.

• [Full-connected Layer]
  - J. Y. Lee, J. Y. Seo, S. J. Park, H. Lee, and Y. H. Lee, "Hardware Accelerator for Real-time Image Classification," The 2024 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, USA, Dec. 11-13, 2024 [Scopus].
  - 서정윤, 이종윤, 박성준, 이하림, "Implementation and Evaluation of fully-connected network on Hardware using Verilog HDL," 한국정보기술학회 하계학술대회, 2024. 

• [RLC based Fully-connected Layer] 이종윤, 이하림, "Evaluation of RLC Compression for Improving Computational Efficiency and Reducing Memory Usage," 한국통신학회 하계학술대회, 2025.

• [Lightweight Fully-connected Network][Quantization][LRA] J. Y. Seo, J. Y. Lee, H. Lee, "Design of Lightweight Fully-connected Network in Hardware using Learning-based Low-rank Approximation and Quantization Techniques," The Transactions of the Korean Institute of Electrical Engineering, 2025 [Scopus].

• [CNN] J. Y. Lee, J. Y. Suh, S. J. Park, H. Lee*, "Design of Hardware Accelerator of Convolution Layer using Verilog HDL," The Transactions of the Korean Institute of Electrical Engineers (KIEE), 2025 [Scopus].

• [Transpose Convolution] J.Y. Lee(=), J.Y. Seo(=), H. Lee, and H. W. Lee, "Implementation of Transpose Convolution Layer on FPGA,"  12th International Conference on Electrical and Electronics Engineering (ICEEE), Istanbul, Turkey, Sept. 24-26, 2025 (= means "equal contribution").

Design of AI Hardware Inference on FPGA.

Development of Abstractive Summary System using Large-Language Model.

• Programming skill set: Python, PyTorch, C++

• Deep Learning Networks: Transformer, BERT, GPT, KoBART, etc.

• Domestic Journal
  1. H.J. Choi and H. Lee, "Development of Cosine Dissimilarity-Based Article Recommendation System Using LLM-generated Abstractive Summary," submitted to The Journal of Korean Institute of Communication and Information Science [Scopus].

Development of Framework to Generate Synthesis Data with the Consideration of Human Privacy.

N-Article Summary Recommendation System with Low Correlation, 2024, Capstone Design Fair.

Patent Trend Analysis of Natural Language based Generative AI and Establishing a Patent Strategy to alleviate Hallucination, 2023, Campus Patent Universiade.

Samsung AI Challenge (3D Metrology), 2022, DACON.

Bigdata Analysis Engineer (빅데이터분석기사, BDA), 2025

Capstone Design Fair, "TextSnack: LLM-based Abstractive Summarization System," Silver Prize, 2024. 

Campus Patent Universiade, "Natural Language Model based Generative AI", Excellence Prize, 2023 (link).

Appropriate Technical Ideas, Bronze Prize, 2021.

Design of AI Hardware Accelerator Combining Binarized Neural Network and Fully Connected Network for Balancing model Compression and Performance.

Python, C, and Verilog HDL.

ADsP (Advanced Data Analytics Semi-Professional, 빅데이터[준전문가]), 2024.

Implementation of New Article Generation System Combining Abstractive Summaries.

 Python, C  and Pytorch

Evaluation of Various Multipliers for Fully-connected Network on FPGA.

Design of AI Hardware Accelerator for various Deep Neural Networks using Verilog HDL.

Verilog HDL, C, Python.